Metal Oxide Semiconductor (MOS) transistors include a substrate, a source, a drain and a channel positioned between the source and drain on the substrate. Routinely, a gate stack is located above the channel, the gate stack being composed of a gate oxide layer or gate electrode located directly above the channel, a gate conductor material above the gate oxide layer, and sidewall spacers. The sidewall spacers protect the sidewalls of the gate conductor.
Some transistor source/drain are recessed below the substrate surface and have epitaxy layers of silicon-containing materials deposited thereon, while no epitaxy layers are formed on the dielectric areas. Various processes, such as selective epitaxy, are used to create a silicon-containing epitaxial layer on the source/drain. A typical selective epitaxy process involves a deposition reaction and an etch reaction. During the deposition process, the epitaxial layer is formed on a monocrystalline surface while a polycrystalline layer is deposited on at least a second layer, such as an existing polycrystalline layer and/or an amorphous layer. However, certain selective epitaxy processes, such as silicon carbon (or Si:C), which use stronger etch components, could damage the sidewall of the recessed areas. These selective epitaxy processes generally incorporate a pre-treatment process on the source/drain to improve filling of those recessed areas and to protect their sidewalls.
Typical pre-treatment processes include selectively growing silicon. By selective growth, it is generally meant that the silicon-containing film grows on a substrate which includes more than one material on the substrate surface, and the silicon-containing film selectively grows on a surface a first material of said substrate, with minimal to no growth on a surface of a second material of said substrate. The silicon layer which results from the typical selective growth pre-treatment process is non-conformal, and therefore, weak points in the layer are present, typically on the sidewall. Such non-conformal growth can cause the side wall to become over etched, thereby creating an undercut when etching away the unwanted deposition on the gate top to achieve selectivity. Moreover, non-conformal growth requires longer subsequent depositions to compensate for the weakness in the silicon layer. However, longer depositions also produce thicker silicon layers in other areas where weak points do not exist.
As will be understood by those skilled in the art, weak points can be found in the areas close to the corner of the recess, typically where source/drain extension regions are located. Source/drain extensions are critical for transistor operation since they form the electrical connection between the source/drain and the channel. Any void or defect in this region can result in a dead transistor. Source/drain extensions are generally heavily implanted and, therefore, it is believed that the silicon-containing layers disposed on these regions are more easily etched away. In addition, defects in the source/drain extension area would reduce the stress delivered to the channel by any stressors deposited in the source and drain.
The point at which the recessed source/drain areas and spacers meet are generally considered the most critical and weak points of the transistor. Accordingly, there is a need for a pre-treatment process by which a conformal silicon-containing layer can be formed on the recessed source/drain areas of transistors.